A radio communication device represented by a cellular phone can include a PLL (Phase Lock Loop) circuit for generating a local oscillator (hereinafter referred to as LO) signal. In recent years, an ADPLL (All Digital Phase Lock Loop) circuit where whole processing is performed by digital circuits is often implemented.
In the ADPLL circuit, a time to digital converter (hereinafter referred to as TDC) for converting a phase difference between the generated LO signal and a reference signal outputted from the outside to a digital value is used. In a general conventional TDC, delay elements such as inverters are connected in series. However, the delay time may vary due to a variation of semiconductor manufacturing, process and so on. Therefore, it is necessary to normalize phase difference information by performing complex operations. As a result, there are problems that the volume of the PLL becomes large and the consumption power increases.